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NEW QUESTION: 1
MPLS LDP IGP synchronization is configured on a link. The OSPF adjacency on that link is UP but MPLS LDP synchronization is not achieved. Which statement about this scenario is true?
A. The router advertises the link in its router LSA with max-metric.
B. The router excludes the link from its OSPF LSA type 1.
C. The router flushes its own router LSA.
D. The router advertises the link and OSPF adjacency as it would when the synchronization is achieved.
E. The router advertises an LSA type 2 for this link, with the metric set to max-metric.
Answer: A
Explanation:
To enable LDP-IGP Synchronization on each interface that belongs to an OSPF or IS-IS process, enter the mpls ldp sync command. If you do not want some of the interfaces to have LDP-IGP Synchronization enabled, issue the no mpls ldp igp sync command on those interfaces. If the LDP peer is reachable, the IGP waits indefinitely (by default) for synchronization to be achieved. To limit the length of time the IGP session must wait, enter the mpls ldp igp sync holddown command. If the LDP peer is not reachable, the IGP establishes the adjacency to enable the LDP session to be established. When an IGP adjacency is established on a link but LDP-IGP Synchronization is not yet achieved or is lost, the IGP advertises the max-metric on that link.
Reference: http://www.cisco.com/c/en/us/td/docs/ios/12_0s/feature/guide/fsldpsyn.html
NEW QUESTION: 2
HOTSPOT
Match each technology to its description.
Answer:
Explanation:
Explanation:
http://h71000.www7.hp.com/doc/83final/b9073_90111/apas13.html The LPMC monitor, within the Support Tools Manager (STM) diagnostics, generates Information events for all cache errors that are detected. After three errors (Threshold) have been detected on a processor in 1440 minutes, or a 24-hour period of time (Period), the monitor deactivates that particular processor, marks it for deconfiguration on the next system reboot, and generates a SERIOUS event. After the failed processor is deactivated, the LPMC monitor attempts to activate one of the inactive Instant Capacity processors, if any are available. This method ensures the processing power of the system is unchanged.
A default value of "three" is assigned to Threshold, except for the PCX-W+ family of processors, which has a value of "five" assigned. The default value assigned to a Period is 1440 minutes, or 24 hours, in all possible processor configurations.
An inactive processor under warranty or support automatically replaces a failed processor. HP also services and replaces any failed processor.
http://www.techrepublic.com/whitepapers/mca-error-recovery-hp-ux-feature-for-recovering-frommachinecheck-aborts/354967
HP Integrity servers provide superior reliability and availability. Nevertheless, even the best of computers can occasionally experience hardware problems that lead to unplanned downtime. Some of these problems are caused by transient events such as an alpha particle strike on memory, cache, or a processor data structure.
Intel Itanium-based servers support an advanced architecture that allows the system to contain, correct, and signal machine check errors. Many of these errors are corrected by the platform without operating system intervention. When the platform cannot correct an error, it will be handed off to the operating system. To further enhance the superior reliability of HP Integrity servers, the HP-UX MCA Error Recovery feature adds the ability to recover from some of these Machine Check Aborts (MCAs).
http://dl.acm.org/citation.cfm?id=1057740 Soft errors are functional failures resulting from the latching of single-event transients (transient voltage fluctuations at a logic node or SETs) caused by high-energy particle strikes or electrical noise. Due to technology scaling and reduced supply voltages, they are expected to increase by several orders of magnitude in logic circuits. Both combinational and sequential logic circuits are expected to be affected. Many different latch designs to prevent soft errors due to particle strikes on the latch nodes have been proposed. We review these designs and compare them based on their robustness and their power and performance overheads. We also propose new latch designs, the best of which is vulnerable only to a single-event, multiple-upset without any delay overhead and consumes only 40% power of a standard latch. We expect this work will help designers to select latches for applications where soft error is an important design metric.
http://en.wikipedia.org/wiki/Montecito_(processor)
Advanced compensation for errors in cache, for reliable operation under mission-critical workloads. This was code-named Pellston technology during development, and has recently been renamed Intel Cache Safe Technology
NEW QUESTION: 3
A. Option B
B. Option E
C. Option C
D. Option A
E. Option D
Answer: D
Explanation:
Use SQL Profiler to trace all queries that are processing on the server. Filter queries that have a Duration value of more than 1,000.
Incorrect:
Not B: The SQL Server lock monitor is responsible for implementing the logic to detect a blocking scenario if the 'blocked process threshold' value is greater than 0. However, the lock monitor only wakes up every 5 seconds to detect this condition (it is also looking for other conditions such as deadlocks). Therefore, if you set a 'blocked process threshold' value to 1, it will not detect a process that has been blocking for 1 second. The minimum time it can detect a blocked process is 5 seconds.
Not E: The Traceflag 1222 Shows Deadlocks, not the Duration of an query.
References: https://docs.microsoft.com/en-us/sql/tools/sql-server-profiler/sql-server-profiler
NEW QUESTION: 4
True or False, Flow-action-based dialog requires that a dialog rule be referenced from the assignment and flow action within the workflow diagram.
A. True
B. False
Answer: B